1. Field of the Invention
Embodiments of the invention relate to a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Related Art
Silicon carbide (SiC) semiconductors have a breakdown field strength that is higher than that of silicon (Si) semiconductors and enable reduction of the ON resistance, which is inversely proportional to the breakdown field strength. Thus, silicon carbide semiconductors have recently gained attention as an optimal semiconductor in low-loss power devices. The development of, for example, SiC-power metal oxide semiconductor field effect transistors (MOSFETs) having a low ON resistance and fast switching speed as a semiconductor device that uses a silicon carbide semiconductor (hereinafter, silicon carbide semiconductor device) has progressed.
In metal oxide semiconductor (MOS) insulated gate silicon carbide semiconductor devices, a MOS gate structure is formed that has, as a gate insulating film, an oxide film (SiO2 film) formed by thermal oxidation on a surface of a silicon carbide semiconductor base (semiconductor chip) constituted by a silicon carbide semiconductor substrate (semiconductor substrate formed using a silicon carbide semiconductor). Nonetheless, when the gate insulating film is formed on the surface of the silicon carbide semiconductor base by thermal oxidation, defects (interface state) are formed in large numbers near a junction interface of the gate insulating film and a silicon carbide semiconductor portion (hereinafter, SiO2/SiC interface), making the interface state density (Dit) rise. Thus, the problems of decreased channel mobility, increased ON resistance, and increased conduction loss occur.
A method by which the interface state density of the SiO2/SiC interface is reduced by forming an oxide film on a silicon carbide semiconductor substrate by thermal oxidation in an atmosphere that includes nitrous oxide (N2O) or nitric oxide (NO) has been proposed as a method of solving these problems (for example, refer to Published Japanese-Translation of PCT Application, Publication No. 2004-511101). Formation of an oxide film that becomes a gate insulating film by thermal oxidation in an atmosphere that includes nitrous oxide or nitric oxide enables the interface state density of the SiO2/SiC interface to be made 2×1012 cm−2 eV−1 or lower, realizing high channel mobility. Therefore, in a SiC-MOSFET, a MOS gate structure may be formed that uses a good quality oxide film as a gate insulating film.
A SiC-vertical MOSFET of a planar gate structure will be described as an example of a structure of a conventional silicon carbide semiconductor device. FIG. 6 is a cross-sectional view of the structure of a conventional silicon carbide semiconductor device. In the conventional silicon carbide semiconductor device depicted in FIG. 6, on a front surface of an n+-type silicon carbide substrate 101 that becomes an n+-type drain region, an n−-type silicon carbide epitaxial layer that becomes an n−-type drift layer 102 and a p−-type epitaxial semiconductor layer that becomes a p−-type well layer 104 are sequentially deposited. Hereinafter, a stacked base formed by sequentially stacking the n−-type drift layer 102 and the p−-type well layer 104 on the n+-type silicon carbide substrate 101 will be regarded as a silicon carbide semiconductor base.
On a front surface side (surface of a p−-type well layer 104 side) of the silicon carbide semiconductor base, a MOS gate structure constituted by a p-type semiconductor region 103, the p−-type well layer 104, a p+-type contact region 105, an n+-type source region 106, a gate insulating film 108, and a gate electrode 109 is provided. The p-type semiconductor region 103 and the p−-type well layer 104 function as a base region. An interlayer insulating film 110 is provided so as to cover the gate electrode 109. In a contact hole that penetrates the interlayer insulating film 110 in a depth direction, a nickel silicide (NiSi) layer 111 forms an ohmic contact (electrical contact portion) with a silicon carbide semiconductor portion. On the interlayer insulating film 110 and the nickel silicide layer 111, a source electrode 112 is provided.
The source electrode 112 is electrically connected to the p+-type contact region 105 and the n+-type source region 106, via the nickel silicide layer 111 and is electrically insulated from the gate electrode 109 by the interlayer insulating film 110. On an entire rear surface (surface on the n+-type silicon carbide substrate 101 side, i.e., rear surface of the n+-type silicon carbide substrate 101) of the silicon carbide semiconductor base, a rear electrode 113 that becomes a drain electrode is provided. Reference numeral 107 is an n−-type junction field effect transistor (JFET) region provided at a portion of the n−-type drift layer 102 beneath the gate electrode 109 (a portion facing the gate electrode 109, via the gate insulating film 108) and between adjacent p−-type well layers 104. Reference 114 is a passivation protective film.
A method of manufacturing the conventional silicon carbide semiconductor device will be described. First, on the front surface of the n+-type silicon carbide substrate 101 that becomes the n+-type drain region, the n−-type drift layer 102 doped with 5×1015/cm3 of nitrogen (N) is deposited (formed) by epitaxial growth to have thickness of 10 μm. The p-type semiconductor region 103 is selectively formed in the surface of the n−-type drift layer 102 by ion implantation of a p-type impurity. On the n−-type drift layer 102, the p−-type well layer 104 doped with 5×1015/cm3 of aluminum (Al) is deposited by epitaxial growth so as to cover the p-type semiconductor region 103 and have a thickness of 0.5 μm.
The JFET region 107 is selectively formed in the p−-type well layer 104 by ion implantation of nitrogen, the JFET region 107 penetrates the p−-type well layer 104 in the depth direction (base depth direction) and reaches the n−-type drift layer 102. Next, the n+-type source region 106 is selectively formed in the p−-type well layer 104 and away from the JFET region 107 by ion implantation of phosphorus (P). Further, the p+-type contact region 105 is selectively formed in the p−-type well layer 104 by ion implantation of aluminum and contacts the n+-type source region 106. Next, activation annealing (heat treatment) is performed at temperature of 1600 degrees C. in an atmosphere of argon (Ar).
Next, by thermal oxidation in an atmosphere of nitrous oxide, on a surface of a portion of the p−-type well layer 104 between the n+-type source region 106 and the JFET region 107, the gate insulating film 108 is formed to have a thickness of 70 nm. A poly-silicon (poly-Si) layer that becomes the gate electrode 109 is formed on the gate insulating film 108. Next, on the entire front surface of the silicon carbide semiconductor base, the interlayer insulating film 110 is formed so as to cover the gate electrode 109. A contact hole is formed by photolithography and etching to penetrate the interlayer insulating film 110 in the depth direction whereby the p+-type contact region 105 and the n+-type source region 106 are exposed in the contact hole.
On the silicon carbide semiconductor portion exposed in the contact hole, a nickel (Ni) film is formed, and the nickel silicide layer 111 is formed by sintering (heat treatment). Next, on the interlayer insulating film 110 and the nickel silicide layer 111, an aluminum layer that becomes the source electrode 112 is deposited to have a thickness of 5.0 μm. On the source electrode 112, a polyimide layer that becomes the passivation protective film 114 is formed and the passivation protective film 114 is hardened (cured) by heat treatment at a temperature of 380 degrees C. Thereafter, on the rear surface of the silicon carbide semiconductor base, the rear electrode 113 is formed, completing the SiC-vertical MOSFET depicted in FIG. 6.